1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a method for controlling a power supply voltage and, in particular, to a semiconductor integrated circuit device and a method for controlling a power supply voltage that can control the power supply voltage of the semiconductor integrated circuit device to be an optimum power supply voltage in a short time.
2. Description of Related Art
There is included DVFS (Dynamic Voltage and Frequency Scaling) among systems for reducing power consumption of a semiconductor integrated circuit device using a CMOS (Complementary Metal Oxide Semiconductor) logic gate. DVFS is a system that controls a power supply voltage depending on a required operating speed (clock frequency). In order to efficiently reduce power consumption in DVFS, it is necessary to control a power supply voltage to be an optimum one in the shortest time and at the highest accuracy possible when the required operating speed is changed.
As a system for controlling a power supply voltage in DVFS, there is a system that determines whether an operating speed of a target semiconductor integrated circuit device satisfies a required speed or not using a delay monitor, and that controls a power supply voltage depending on the determined result. FIG. 31 is a block diagram showing a power supply voltage controller disclosed in Japanese Unexamined Patent Application Publication No. 2002-100967. In the power supply voltage controller shown in FIG. 31, a time period for controlling a power supply is reduced by comparing an operating speed of a circuit with a required operating speed by a delay monitor, and adjusting a voltage control amount depending on the compared result.
A power supply voltage controller 500 shown in FIG. 31 has a semiconductor circuit (LSI) 509 as a target circuit to which a controlled power supply voltage VDD is supplied, an input signal generation circuit 510, a monitor circuit 504 that monitors a delay characteristic of a critical path of the LSI 509, a delay detection circuit 505, and a power supply voltage control circuit 508. The power supply voltage control circuit 508 has a control circuit 506 and a voltage generation circuit 507. The input signal generation circuit 510 has a clock generation circuit 511 and a frequency divider circuit 503, and the clock generation circuit 511 is composed of a PLL circuit 501 and a selector 502.
The PLL circuit 501 incorporates an oscillator (VCO) controlled by a voltage, and locks an oscillation frequency of the oscillator based on, for example, an LSI drive clock CLK input from outside. A plurality of VCO outputs of the PLL circuit 501 is connected to each input of the selector 502, and a first output and a second output of the selector 502 are connected to inputs of the frequency divider circuit 503. The selector 502 outputs a signal inφi from the second output whose phase is delayed only by i with respect to a signal inφ0 transmitted to the first output thereof. This phase i can be represented with an arbitrary phase angle within 0 to 2π.
The frequency divider circuit 503 frequency-divides the signal inφ0 from the first input at a predetermined frequency division ratio, and generates a signal outφ0 to be supplied to the monitor circuit 504. In addition, the frequency divider circuit 503 frequency-divides the signal inφi from the second input at, for example, the same predetermined frequency division ratio, and generates a reference signal outφi to be supplied to the delay detection circuit 505. This reference signal outφi is generated as a signal that is delayed only by a variable delay value D with respect to the signal outφ0 to be supplied to the monitor circuit 504. The monitor circuit 504 is configured as a circuit that has a power supply voltage delay characteristic equivalent to a signal transmission path selected as a critical path in the semiconductor circuit 509, and it operates with the supply of a power supply voltage VDD by the voltage generation circuit 507, transmits the signal outφ0 output from the frequency divider circuit 503, and outputs a delayed signal outφ0′ to the delay detection circuit 505.
The delay detection circuit 505 detects a phase difference between the reference signal outφi and the output signal outφ0′ of the monitor circuit 504, generates an x-bit delay detection signal (x is an arbitrary natural number) depending on a detected result, and outputs it to the control circuit 506. The control circuit 506 controls the voltage generation circuit 507 based on the delay detection signal from the delay detection circuit 505, and changes a value of the supply voltage VDD to the LSI 509 and the monitor circuit 504.
Namely, when the output outφ0′ of the monitor circuit 504 is output later than a predetermined delay value specified by the reference signal outφi, the control circuit 506 outputs a request signal for increasing the supply voltage VDD to the voltage generation circuit 507, while, on the contrary, when the output outφ0′ of the monitor circuit 504 is output earlier than the predetermined delay value or when earlier than a delay value obtained by further subtracting a certain margin from the predetermined delay value, the control circuit 506 outputs a request signal for decreasing the supply voltage VDD to the voltage generation circuit 507. As a result, the voltage generation circuit 507 generates a new power supply voltage VDD′, and changes the current supply voltage into the new power supply voltage VDD′.
In addition, in Japanese Unexamined Patent Application Publication No. 2009-38128, there is disclosed a technology on a semiconductor integrated circuit device that can suppress malfunction of a main function circuit and that can achieve low power consumption. The semiconductor integrated circuit device disclosed in Japanese Unexamined Patent Application Publication No. 2009-38128 is provided with the main function circuit to which a predetermined drive voltage is supplied when it is driven, detection means that detects a change of a characteristic of the main function circuit, and determination means that determines the drive voltage supplied to the main function circuit based on the detected result of the change of the characteristic of the main function circuit by the detection means, as well as having a predetermined main function. Moreover, the semiconductor integrated circuit device is provided with switch means that switches the supply voltage so that the drive voltage determined by the determination means may be supplied to the detection means when the main function circuit is driven and so that the predetermined voltage may be supplied thereto when the change of the characteristic of the main function circuit is detected.
In the semiconductor integrated circuit device disclosed in Japanese Unexamined Patent Application Publication No. 2009-38128, the supply voltage is switched so that the determined drive voltage may be supplied to the detection means that detects the change of the characteristic of the main function circuit due to a change of a usage environment, etc when the main function circuit is driven and so that the predetermined voltage may be supplied thereto when the change of the characteristic of the main function circuit is detected. As a result of this, a degree of degradation of the detection means and that of wires of the main function circuit become substantially the same as each other, and it becomes unnecessary to add a constant margin to a correction voltage, thus enabling to suppress the malfunction of the main function circuit and to achieve low power consumption.